28.4 A 12b 330MS/s pipelined-SAR ADC with PVT-stabilized dynamic amplifier achieving <1dB SNDR variation

Hai Huang, Sudipta Sarkar, Brian Elies, Yun Chiu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In high-speed pipeline or pipelined-SAR ADCs, conventional opamp-based residue amplifiers consume significant amounts of power due to stringent settling speed and accuracy requirements. A recent alternative approach employs a dynamic amplifier [1] to achieve a more efficient form of settling, stemming from the fact that slewing is more power efficient than exponential settling (Fig. 28.4.1). For example, at 6b accuracy, the setting time of a dynamic amplifier is about a quarter of that of a conventional opamp (non-slewing) with the same bias current. However, the efficiency of the dynamic amplifier is accompanied by a few undesirable features such as ill-defined gain, and PVT and clock jitter sensitivity. In particular, as the voltage gain of a dynamic amplifier relates to the non-constant transconductance, load capacitance and slewing time (gmA, CLA and tA, respectively, in Fig. 28.4.1), it can drift dramatically with PVT variations. One way to compensate for gain instability is to employ continuous background calibration. However, most of these calibrations require some constraints on the statistical property of the input signal and suffer from long convergence time and design complexity. This paper presents a simple analog approach to effectively stabilize the voltage gain over PVT variations.

Original languageEnglish (US)
Title of host publication2017 IEEE International Solid-State Circuits Conference, ISSCC 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages472-473
Number of pages2
Volume60
ISBN (Electronic)9781509037575
DOIs
StatePublished - Mar 2 2017
Event64th IEEE International Solid-State Circuits Conference, ISSCC 2017 - San Francisco, United States

Other

Other64th IEEE International Solid-State Circuits Conference, ISSCC 2017
CountryUnited States
CitySan Francisco
Period2/5/172/9/17

Fingerprint

Operational amplifiers
Calibration
Bias currents
Transconductance
Jitter
Clocks
Capacitance
Pipelines

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Huang, H., Sarkar, S., Elies, B., & Chiu, Y. (2017). 28.4 A 12b 330MS/s pipelined-SAR ADC with PVT-stabilized dynamic amplifier achieving <1dB SNDR variation. In 2017 IEEE International Solid-State Circuits Conference, ISSCC 2017 (Vol. 60, pp. 472-473). [7870466] Institute of Electrical and Electronics Engineers Inc.. DOI: 10.1109/ISSCC.2017.7870466

28.4 A 12b 330MS/s pipelined-SAR ADC with PVT-stabilized dynamic amplifier achieving <1dB SNDR variation. / Huang, Hai; Sarkar, Sudipta; Elies, Brian; Chiu, Yun.

2017 IEEE International Solid-State Circuits Conference, ISSCC 2017. Vol. 60 Institute of Electrical and Electronics Engineers Inc., 2017. p. 472-473 7870466.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Huang, H, Sarkar, S, Elies, B & Chiu, Y 2017, 28.4 A 12b 330MS/s pipelined-SAR ADC with PVT-stabilized dynamic amplifier achieving <1dB SNDR variation. in 2017 IEEE International Solid-State Circuits Conference, ISSCC 2017. vol. 60, 7870466, Institute of Electrical and Electronics Engineers Inc., pp. 472-473, 64th IEEE International Solid-State Circuits Conference, ISSCC 2017, San Francisco, United States, 5-9 February. DOI: 10.1109/ISSCC.2017.7870466
Huang H, Sarkar S, Elies B, Chiu Y. 28.4 A 12b 330MS/s pipelined-SAR ADC with PVT-stabilized dynamic amplifier achieving <1dB SNDR variation. In 2017 IEEE International Solid-State Circuits Conference, ISSCC 2017. Vol. 60. Institute of Electrical and Electronics Engineers Inc.2017. p. 472-473. 7870466. Available from, DOI: 10.1109/ISSCC.2017.7870466

Huang, Hai; Sarkar, Sudipta; Elies, Brian; Chiu, Yun / 28.4 A 12b 330MS/s pipelined-SAR ADC with PVT-stabilized dynamic amplifier achieving <1dB SNDR variation.

2017 IEEE International Solid-State Circuits Conference, ISSCC 2017. Vol. 60 Institute of Electrical and Electronics Engineers Inc., 2017. p. 472-473 7870466.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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