A 23-mW 24-GS/s 6-bit Voltage-Time Hybrid Time-Interleaved ADC in 28-nm CMOS

Benwei Xu, Yuan Zhou, Yun Chiu

Research output: Research - peer-reviewArticle

Abstract

This paper presents a power- and area-efficient 16-way time-interleaved (TI) analog-to-digital converter (ADC) achieving 24-GS/s conversion speed and 6-bit resolution in 28-nm CMOS. A voltage-time hybrid pipeline technique exploiting the comparator input-voltage-output-time dependency is reported to enhance the throughput of successive-approximation-register (SAR) ADCs. A reference-buffer-free capacitive digital-to-analog (CDAC) converter is utilized to mitigate the crosstalk problem in TI-ADCs. Timing mismatches between individual sub-ADCs are estimated with a reference-ADC dithering technique and corrected by digitally controlled delay lines (DCDL). The techniques collectively enabled a very compact design, obviating any input buffer or hierarchical sampling structures. The ADC core consumes 23 mW and occupies an area of 0.03 mm². A signal-to-noise plus distortion ratio (SNDR) of 35 dB and a spurious-free dynamic range (SFDR) of 54 dB were measured for a 40-MHz input. For a Nyquist input, the prototype measured an SNDR of 29 dB and an SFDR of 41 dB with all timing mismatch spurs suppressed below -50 dBc after skew calibration.

LanguageEnglish (US)
JournalIEEE Journal of Solid-State Circuits
DOIs
StateAccepted/In press - Jan 23 2017

Fingerprint

Digital to analog conversion
Electric potential
Electric delay lines
Crosstalk
Pipelines
Throughput
Calibration
Sampling

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

A 23-mW 24-GS/s 6-bit Voltage-Time Hybrid Time-Interleaved ADC in 28-nm CMOS. / Xu, Benwei; Zhou, Yuan; Chiu, Yun.

In: IEEE Journal of Solid-State Circuits, 23.01.2017.

Research output: Research - peer-reviewArticle

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